This invention relates to a nonvolatile semiconductor storage device and a method for using it, and more particularly to a multi-level memory, and its usage, which can store multi-level (multi-value) data in memory cells made of stacked MOS transistors.
A flash memory for storing multi-level data is disclosed in detail in ISSCC '95 Digest of Technical Papers, p. 133, for example. The memory has an architecture using flash cells as its reference cells to control the current flow into the reference cells and to cope with the read-out potential in accordance with the distribution of threshold values of the cells.
A process for reading data from a NAND flash memory includes random access for reading data of one row of memory cell arrays and for storing it in registers, and subsequent reading of the storage of the registers. When a four-value memory is to be read three times, reading and conversion into a two-value data need the time EQU 3t.sub.R +3t.sub.S +t.sub.conv
where t.sub.R is the random access time, t.sub.S is the time for reading registers, and t.sub.conv is the time for conversion into a two-value data. In a particular case where the random access time t.sub.R is 10 .mu.S, the register reading time t.sub.S is 25.6 .mu.S for reading 512 bytes in 50 ns, and the time t.sub.conv for conversion into a two-value data is 5 .mu.S, the total time for reading thrice and for conversion into two values amounts in EQU 10.times.3+25.6.times.3+5=111.8 .mu.S
The above multi-level memory involves the following problems.
(1) A 2.sup.n -value memory needs n sense amplifiers. Specifically, a four-value memory needs tow sense amplifiers, and an eight-value memory needs three sense amplifiers. Thus the multi-level memory requires a larger area for sense amplifiers.
(2) The number of reference cells is fixed at the time of its design and cannot be flexibly changed later. In a particular case where the number of reference cells is four, the memory must be a four-value memory even if the cells are uniform enough to realize a more-value memory. In another case where a four-value memory cannot be realized due to varieties in process parameters during fabrication, although it will be used as a two-value memory, all the sense amplifiers and other circuit elements intended for use with the four-value memory become invalid, and result in an substantial increase in cost as compared with an originally two-value memory.
(3) The area occupied by sense amplifiers is too large to exactly cope with the distribution of cells within the chip.
(4) Reading from a NAND flash memory takes time against the demand for high-sped reading.